For people interested in how computers work bottom-up.

Tuesday, May 09, 2006

CPU Project Calendar (sortof)

Looking at this whole project at once is a bit intimidating, so I split it up into a few different stages.

  1. Overall Architecture
    1. Concrete design parameters
    2. Number of functional units and their partitioning
    3. Major units
    4. Busses between units
    5. ISA (likely to be a subset of the M-word)
    6. Scheduling algorithm
    7. Do some quantitative analysis to back up design choices
    8. At this point, I should have a bunch of nifty drawings and all-around fuzzy feelings about the project
  2. Basic Processor
    1. Implement instruction decode for basic arithmetic instructions
    2. Implement 4-issue scheduling hardware
      1. Dependency FIFOs
      2. Register file
      3. Re-Order Buffer
      4. Write-Back bus arbitrator
    3. Implement basic ALU functional units
    4. Bypass hardware
    5. Instruction memory (trivial)
    6. Trackers, trackers, and more trackers
      1. Make sure to have good debugging information
      2. Possibly implment a transaction checker
    7. At this point, I should have a good testbench environment and be able to calculate the fibbonacci sequence along with some other basic programs
  3. Branches
    1. Implement branch functional unit
      1. branch
      2. jump
      3. trap
    2. Implement branch prediction unit
      1. Branch prediction table
      2. Branch target buffer
      3. Return address stack
    3. Implement branch-misprediction rollback mechanism (should be trivial)
  4. Load/Store + Cache
    1. Implement Load/store functional unit
    2. Implement data and instruction caches
    3. Implement bus interface
    4. Implement cache system instructions
  5. TLB + interrupts/exceptions + Finish implementing all instructions
    1. TLB
    2. interrupts/exceptions
    3. finish all instructions
  6. Floating Point Units?
    1. This would be nifty. We'll see how much space is left.
  7. At this point, I should have a working processor. Pat self on back.


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