For people interested in how computers work bottom-up.

Monday, May 01, 2006

A Complexity-Effective Dynamic Scheduling Algorithm

I found this paper online:

This method uses register renaming along with dependency checking in instruction dispatch to reduce complexity in the wakeup-select logic (reservation stations). A FIFO is setup for each issue slot, instructions are issued to FIFOs so that dependency chains are located in FIFOs. This means that instructions only need to be checked at the head of the FIFO if they are ready to be dispatched to a function unit.

This could greatly reduce the cycle-time and resources used by the scheduler in an FPGA CPU.


Blogger Tommy Thorn said...

Thanks for the link. A full literature search would be overwhelming, so a short list of FPGA relevant papers is nice.

I haven't read all the papers yet, but I've been playing with the idea of a partitioned register file.

One of the problems of OoO is the need for write ports. Read ports are much cheaper in FPGAs so my thought was to associate a small regfile with each pipe and rename registers as they are issued to each pipe. Cross-pipeline accesses would perhaps pay a penalty, but this approach scales better than adding write ports. The frontend register renaming & completion will a bottleneck, but at least the renaming table is much narrower than the register file itself.

Maybe a blog comment isn't a good place to discuss these things.

8:42 AM  

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