For people interested in how computers work bottom-up.

Sunday, April 30, 2006


I started up this blog to post updates on the various projects I undertake. I enjoy designing and implementing CPU designs and the like. People who truly enjoy something like that are far and few inbetween. Hopefully I can provide some interesting content to people and even get some feedback on the stuff I work on.

I learned synchronous digital design not quite a year ago. Ever since I've been focusing on implementing my own computer system and porting Linux. I've created several different processors in this time. Most of them are based on the MIPS instruction set, two of them weren't. Of the two that differed, one was a Subtract and Branch if Negative machine. Very slow, but with enough time, just as capable as any other cpu.

The other was a 16-Bit dual issue superscalar processor I designed specifically for a high clock speed on an FPGA. I was able to sanely fit 9 of these processor cores in one Spartan 3 FPGA. Theoretically it should be very fast, however it's programming model is a major pain in the bum. One core alone would operate at 180MHz on an FPGA. The nine core version operated at about 150MHz.

So now I'm trying to figure out the most cost-effective/performance cpu design, for the FPGA development board I have, that can run Linux. Then I will port Linux to the board, say "Woop-de-doo", and pat myself on the back for a job well done.


Blogger eti said...

hello luke valenty.
wonderful your all-ttl CPU design "sustract and brainch if negative...
i am myself struggling with Myke predko's ( in his book "digital Electronics Guidebook ") design of a 38 ttl chips CPU design ( i would be happy to send you these schematics i there was a way to mail you. ( you can contact me at ) and perhaps you mighe be willing to share the shematics of your substract and branch CPU....
etienne delacroix. montevideo, uruguay

11:14 PM  

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