Dynamic Instruction Scheduling Algorithms
For my latest processor design, I want to do a modern processor design. This can mean many things. To me, it means it must have the following qualities:
- Out of Order Execution
- Speculative Execution
- At least L1 Cache
- Memory Management Unit
So now I'm researching other alternatives. I would really like to be able to do a four-issue processor, however, I don't think it's possible at this point.
Here are some resources I'm currently reading: